3D-Integrated High-sensitivity Optical Receiver

Team member: Saman Saeedi

Increasing Silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics can bring their performance to unprecedented levels. In this project a 3D-integrated CMOS/Silicon-photonic receiver is presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. We study different trade-offs in designing an optical receiver and how to choose between full-bandwidth TIA front-end and different integrating front-end architectures. The design methodology is supported by measurements of two 3D-integrated prototypes based on a conventional TIA and a double-sampling integrating receiver. The proposed receiver architecture achieves a sensitivity of -14.9dBm and energy efficiency of 170fJ/b at 25Gb/s.

Related Publications

S. Saeedi, S. Menezo, G. Pares, A. Emami, “A 25Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication,” IEEE Journal of Lightwave Technology, 2015.

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S. Saeedi, S. Menezo and A. Emami, “A 25Gbps 3D-Integrated CMOS/Silicon Photonic Optical Receiver with -15dBm Sensitivity and 0.17pJ/bit Energy Efficiency“, IEEE Optical Interconnect Conference (OIC), 2015

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S. Saeedi, A. Emami, “A 25Gb/s 170μW/Gb/s High-Sensitivity Optical Receiver in 28nm CMOS for Low-power Optical Communication“, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2014.

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