Team member: Matthew Loh

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As data rates increase, process, voltage and temperature variations cause sufficient phase mismatch between signal paths to require per-pin phase alignment – even in source-synchronous systems. Due to the high signal densities desired for future interconnect, the power and area overhead of adding dedicated clock and data recovery circuitry to each data pin is prohibitive. Traditional techniques that apply analog approaches to solving this problem (such as PLLs or DLLs) are subject to unacceptable area, power and process variation overheads.

This project involves the development of a novel all-digital clock and data recovery technique for per-pin phase adjustment in high-density, high-performance serial interconnect. Two independently adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase is placed in the middle of the eye to recover the data, while the other is swept across the delay line. The samples produced by the two clocks are compared to generate eye information, which is used to determine the best phase for data recovery. The functions of the two clocks are swapped after the data phase is updated; this ping-pong action allows an infinite delay range without the use of a PLL or DLL. The scheme’s generalized sampling and retiming architecture is used in a sharing technique that saves power and area in high-density interconnect.

Related Publications

M. Loh, A. Emami-Neyestanak, “A 3×9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O“, IEEE Journal of Solid-State Circuits, vol.47, no.3, March 2012, DOI: 10.1109/JSSC.2011.2178557

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M. Loh, A. Emami, “All-Digital CDR for High-Density, High-Speed I/O“, IEEE Symposium on VLSI Circuits, 2010, DOI: 10.1109/VLSIC.2010.5560319

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M. Loh, A. Emami, “All-Digital CDR for High-Density, High-Speed I/O“, IEEE Symposium on VLSI Circuits, 2010, DOI: 10.1109/VLSIC.2010.5560319

[ PDF ]