Ultra-Low-Power Equalization and Crosstalk Cancellation
Team member: Meisam Honarvar Nazari
The increasing demand for high bandwidth interconnection between integrated circuits requires large numbers of I/Os per chip as well as high data rates per I/O. Key limitations in meeting these requirements include channel characteristics and I/O power consumption. Even in short interconnects, the channel attenuation at very high data rates is significant, and using receiver and transmitter equalization can greatly improve the link performance. Parallel data transmission increases the aggregate data rate, but compact traces placed in close proximity suffer from a high level of crosstalk interference. In this project we employ a novel low-power switched-capacitor based equalization technique to efficiently compensate the channel loss. Additionally, we take advantage of this technique to cancel far-end crosstalk (FEXT) at minimal power penalty. The prototype was fabricated in 45nm SOI process and has been tested at data rates up to 20Gb/s.
M. Honarvar, A. Emami-Neyestanak, “A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation“, IEEE Journal of Solid-State Circuits, vol.47, no.10, pp.2420-2432, Oct. 2012[ PDF ]
M. Honarvar, A. Emami-Neyestanak, “A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation“, International Solid-State Cicruits Conference (ISSCC), 2011[ PDF ]
M. Honarvar, A. Emami-Neyestanak, “A Low-Power 20Gb/s Transmitter in 65nm CMOS Technology“, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), vol., no., pp.149-152, 17-19 June 2012[ PDF ]