Increasing bandwidth requirements have pushed the traditionally electrical wireline interconnects within computing systems and data centers to their limits. As data-rates
scale, the shortcomings of electrical channels are becoming more severe. Technology scaling favors I/O circuit performance, but the bandwidth of electrical channels does not scale with the same trend. Several receiver and transmitter equalization techniques have been proposed to overcome this bandwidth limitation. However, these compensation techniques consume considerable power and die area, and, as a result, current high-speed I/O link designs are increasingly becoming power and channel-limited.
Optical interconnects are essential components in data center networks. Energy proportional data centers can achieve significant power savings by reducing power consumption at lower data-rates or when idle. We use adaptive body biasing to present an energy proportional source-synchronous 4-channel WDM-based parallel optical receiver.
Increasing Silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this project a 3D-integrated CMOS/Silicon-photonic receiver is presented. The receiver is specifically designed to take advantage of low-cap 3D integration and advanced silicon photonics.
As data rates increase, process, voltage and temperature variations cause sufficient phase mismatch between signal paths to require per-pin phase alignment – even in source-synchronous systems. This project involves the development of a novel all-digital clock and data recovery technique for per-pin phase adjustment in high-density, high-performance serial interconnect.
The negligible frequency dependent loss of optical channels provides the potential for optical links to fully leverage increased data rates provided through CMOS technology scaling without excessive equalization complexity. A compact low-power optical receiver has been designed to explore the potential of optical signaling for future chip-to-chip and on-chip communication.
The increasing demand for high bandwidth interconnection between integrated circuits requires large numbers of I/Os per chip as well as high data rates per I/O. Key limitations in meeting these requirements include channel characteristics and I/O power consumption. Using receiver and transmitter equalization can greatly improve the link performance.