Team member: Saman Saeedi
Clock multipliers play a key role in design of high-speed electrical and optical links. As the aggregate bandwidth requirement for chip-to-chip interconnects grows, their respective frequency of operation increases. Additionally, high-speed links timing noise heavily depends on jitter performance of the clock multiplier, which takes a low-jitter low frequency reference and generates the high frequency clock for the transceivers. This necessitates design of high-frequency clock generators that have inherently lower jitter and are resilient to noise induced by outside sources such as supply noise or digital switching noise. In this project a first order frequency synthesizer is presented that is suitable for high-speed on-chip clock generation. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a phase interpolator, digital coarse-tuning, and rotational frequency detection for fine-tuning. In this architecture the rising edge of the reference clock is directly injected to the output clock, resetting jitter accumulation similar to an MDLL. Also, first order frequency detection and frequency correction is used, providing unconditional stability. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be 64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.
S. Saeedi, A. Emami, “An 8GHz First-order Frequency Synthesizer for Low-Power On-Chip Clock Generation“, IEEE Journal of Solid-state Circuits, vol. 50, no. 8, pp. 1848-1860, Aug. 2015[ PDF ]
S. Saeedi, A. Emami, “An 8GHz First-order Frequency Synthesizer based on Phase Interpolation and Quadrature Frequency Detection in 65nm CMOS“, IEEE Custom Integrated Circuits Conference (CICC), 2014[ PDF ]