Team member: Meisam Honarvar Nazari
CMOS technology scaling has increased the processing power of microprocessors. This highlights the importance of on-chip wires that carry data between different sections in a processor and also between processor cores in multiple core technology. Another important consequence of scaling is growing wire resistance which coupled with shrinking native gate speeds makes wire delays increasingly large. Previously chip designers could treat on-chip wires as purely capacitive loads of logic gates; these wires had no intrinsic delays of their own. Since gate delays decrease under scaling, we see an ever-increasing disparity between wire and gate delays. Repeaters mitigate the loss problem but do little to improve the energy cost. Moreover, as technology scales, the number of repeaters grows significantly, which increases power consumption and adds complexity. Our goal in this project is to take a close look at on-chip wires scaling and investigates the challenges of on-chip signaling in highly-scaled technologies. We will introduce novel techniques to mitigate these challenges in a power and area efficient manner.
M. Honarvar, A. Emami-Neyestanak, “A 20GB/s 136fJ/b 12.5Gb/s/μm On-Chip Link in 28nm CMOS“, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), vol., no., 2-4 June 2013[ PDF ]
S. Saeedi, A. Emami, “An 8GHz First-order Frequency Synthesizer for Low-Power On-Chip Clock Generation“, IEEE Journal of Solid-state Circuits, vol. 50, no. 8, pp. 1848-1860, Aug. 2015[ PDF ]