Neural Interfaces

Neural interfaces are generally categorized as systems which enable direct communication between the cortex and an external device. Such systems could be used for monitoring and treating neurological disorders like epilepsy, studying and treating neurodegenerative disorders and also for allowing tetraplegic patients to control neuroprosthetic devices. Neural Interfaces will play a vital role in restoring sensory function, communications, and control in impaired humans. Designing low-power circuits and efficient algorithms are essential parts of making these systems robust and wearable.

With respect to Neural Interfaces, our lab focuses on three main areas of research:

 

 

On-Chip Communication Networks and Clocking

Wideband Injection Locking and Quadrature Phase Generation

Injection-locked-oscillators (ILOs) have been used extensively because of their simple implementation and instantaneous locking characteristics. However, their application is hindered by their limited locking range compared with alternative techniques such as PLLs. In this project, PLL and injection locking elements are combined symbiotically to achieve wide locking range while retaining the simplicity of the latter.

Low-power First-order Frequency Synthesizer

Clock multipliers play a key role in design of high-speed electrical and optical links. As the aggregate bandwidth requirement for chip-to-chip interconnects grows, their respective frequency of operation increases. In this project a first order frequency synthesizer is presented that is suitable for high-speed on-chip clock generation. In this architecture the rising edge of the reference clock is directly injected to the output clock, resetting jitter accumulation similar to an MDLL.

On-Chip Interconnects

Our goal in this project is to take a close look at on-chip wires scaling and investigate the challenges of on-chip signaling in highly-scaled technologies. Novel techniques to mitigate these challenges in a power and area efficient manner are introduced.

MICS

VCSEL driver

Team Members: Mayank Raj and Manuel Monge

Increasing bandwidth requirements have pushed the traditionally electrical wireline interconnects within computing systems and data centers to their limits. As data-rates scale, the shortcomings of electrical channels are becoming more severe. Technology scaling favors I/O circuit performance, but the bandwidth of electrical channels does not scale with the same trend. Several receiver and transmitter equalization techniques have been proposed to overcome this bandwidth limitation. However, these compensation techniques consume considerable power and die area, and, as a result, current high-speed I/O link designs are increasingly becoming power and channel-limited.

The lab has worked on an ultralow-power VCSEL transmitter in 32 nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. Driving the VCSEL in this condition increases its inherent nonlinearity. Conventional pre-emphasis techniques cannot compensate for this effect because they have a linear response. To overcome this limitation, a nonlinear equalization scheme is proposed. A dynamic VCSEL modeling technique is used to generate the time-domain optical responses for “one” and “zero” bits. Based on the asymmetry of the two responses, the rising and falling edges are equalized separately. Additionally, instead of using fixed bit delays, the equalization delay is selected based on the bias current of the VCSEL. The efficiency of the proposed modeling and equalization technique is evaluated through simulations and measurements. The transmitter achieves energy efficiency of 0.77 pJ/b at 20 Gb/s and occupies 100 µm × 60 µm active silicon area.

Related Publication

Mayank Raj, Manuel Monge, Azita Emami “A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS,” IEEE Journal of Solid-State Circuits, vol.51, no.8, pp.1734 – 1743, July. 2016

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Location-Broadcasting Chips

We present an alternative approach to microscale device localization based on concepts from nuclear magnetic resonance. In particular, the magnetic-field-dependent precession frequency of nuclear spins allows their location in space to be encoded through the application of magnetic field gradients. This allows MRI to visualize signals from nuclear spins located throughout a specimen with ~100 µm resolution.

WDM-Based Energy Proportional Parallel Optical Receiver

Optical interconnects are essential components in data center networks. Energy proportional data centers can achieve significant power savings by reducing power consumption at lower data-rates or when idle. We use adaptive body biasing to present an energy proportional source-synchronous 4-channel WDM-based parallel optical receiver.

3D-Integrated High-sensitivity Optical Receiver

Increasing Silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this project a 3D-integrated CMOS/Silicon-photonic receiver is presented. The receiver is specifically designed to take advantage of low-cap 3D integration and advanced silicon photonics.

Fully Implantable Glucose and Lactate Sensor

Miniaturization of implantable biosensors for continuous, in vivo monitoring of clinically relevant analytes is an important step toward viability of such devices. While wireless power delivery via on-chip antennas promises miniaturization and realization of minimally invasive devices, it can only support low levels of power consumption. This is due to the significant tissue absorption at high frequencies, small size of the chip and quality factor of on-chip inductors. Therefore, reducing the power consumption of the sensor while maintaining high sensitivity and dynamic range is crucial.

Network-on-Chip Architectures

Network-on-chip (NoC) allows regular layout and hierarchical design, enabling high-core-count system-on-chip (SoC) designs that are capable of addressing future computational demands and challenges. We are investigating architectural and circuit-level approaches to enable the next-generation of efficient, high-performance computing systems.