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Entries by awp-admin
Network-on-chip (NoC) allows regular layout and hierarchical design, enabling high-core-count system-on-chip (SoC) designs that are capable of addressing future computational demands and challenges. We are investigating architectural and circuit-level approaches to enable the next-generation of efficient, high-performance computing systems.
Epilepsy is a common neurological disorder affecting over 50 million people in the world. Approximately one third of epileptic patients exhibit seizures that are not controlled by medication. Despite substantial innovations in anti-seizure drug therapy, the proportion of patients with uncontrolled epilepsy has not changed, emphasizing the need for new treatment strategies. The development of new devices capable of performing a rapid and reliable seizure detection followed by brain stimulation holds great promises for improving the quality of life of millions of people with epileptic seizures worldwide.
As signals in the physical world are ultimately analog in nature, analog-to-digital converters (ADCs) are a key enabling technology for this trend. However, ADC speed and resolution have not kept pace with the stunning improvements in computing power, thus creating a bottleneck which limits the performance and application space of advanced signal processing techniques in physical systems.
Most progressive vision loss occurs when the first layer of the retina (the photoreceptors) is damaged. Retinal prostheses aim to restore vision by bypassing the damaged photoreceptors and directly stimulating the remaining healthy neurons. Our approach uses highly scaled technologies to reduce area and power, and to support hundreds of channels for fully intraocular implants.
Origami implant design is a 3D integration technique which addresses the size and cost constraints in biomedical implants. Large systems can be split into multiple chips and connected using 3D integration techniques to be folded compactly for implantation and unfolded inside the body. Electronics can be partitioned into functional blocks for mass-production and customs implants can be assembled from these relatively cheap modules.
As data rates increase, process, voltage and temperature variations cause sufficient phase mismatch between signal paths to require per-pin phase alignment – even in source-synchronous systems. This project involves the development of a novel all-digital clock and data recovery technique for per-pin phase adjustment in high-density, high-performance serial interconnect.
The negligible frequency dependent loss of optical channels provides the potential for optical links to fully leverage increased data rates provided through CMOS technology scaling without excessive equalization complexity. A compact low-power optical receiver has been designed to explore the potential of optical signaling for future chip-to-chip and on-chip communication.