Injection-locked-oscillators (ILOs) have been used extensively because of their simple implementation and instantaneous locking characteristics. However, their application is hindered by their limited locking range compared with alternative techniques such as PLLs. In this project, PLL and injection locking elements are combined symbiotically to achieve wide locking range while retaining the simplicity of the latter.
Clock multipliers play a key role in design of high-speed electrical and optical links. As the aggregate bandwidth requirement for chip-to-chip interconnects grows, their respective frequency of operation increases. In this project a first order frequency synthesizer is presented that is suitable for high-speed on-chip clock generation. In this architecture the rising edge of the reference clock is directly injected to the output clock, resetting jitter accumulation similar to an MDLL.
Our goal in this project is to take a close look at on-chip wires scaling and investigate the challenges of on-chip signaling in highly-scaled technologies. Novel techniques to mitigate these challenges in a power and area efficient manner are introduced.
Network-on-chip (NoC) allows regular layout and hierarchical design, enabling high-core-count system-on-chip (SoC) designs that are capable of addressing future computational demands and challenges. We are investigating architectural and circuit-level approaches to enable the next-generation of efficient, high-performance computing systems.