MICS Lab | A Low-power 20Gb/s On-Chip Link

Chip Gallery

A Low-power 20Gb/s On-Chip Link

Chip

Technology: 28nm Bulk CMOS
TO Date: 2012
Designer: Meisam Honarvar Nazari
Project: On-Chip Interconnects

Chip Gallery
A 65nm CMOS Living-Cell Dynamic Fluorescence Sensor with 1.05fA Sensitivity at 600/700nm WavelengthsFebruary 24, 2023 -
100Gb/s SiP-CMOS PAM4 TX Using MOSCAP ModulatorsApril 10, 2022 -
100Gb/s SiP-CMOS PAM4 TX Using MOSCAP ModulatorsApril 10, 2022 -
100Gb/s SiP-CMOS PAM4 Transmitter Using MOSCAP ModulatorsApril 10, 2022 -
A 100 Gb/s PAM-4 SiP TX Using EAMs in MZI StructureApril 10, 2022 -
Biofuel-Cell-Based Energy HarvesterApril 10, 2022 -
A 60-Gb/s PAM4 Wireline Receiver Employing Track-and-Regenerate SlicersApril 10, 2022 -
An 8Gbps Adaptive Receiver for RF over FSO in 28nm CMOSApril 10, 2022 -
Wireless 3D Surgical Navigation and Tracking SystemApril 10, 2022 -
A 25Gb/s APD-Based Burst-Mode Optical ReceiverSeptember 23, 2019 -
Fully Implantable Glucose and Lactate SensorSeptember 7, 2017 -
Silicon Photonic Differential Micro-Ring ModulatorSeptember 7, 2017 -
PTAT Temperature Sensor For Micro-Ring Resonator Thermal TuningSeptember 7, 2017 -
WDM-based Energy Proportional Pararllel Optical ReceiverSeptember 7, 2017 -
Low Power VCSEL based Optical TransmitterSeptember 7, 2017 -
3D-Integrated CMOS-Silicon Photonic Optical ReceiverSeptember 7, 2017 -
Low-Power First-Order Frequency SynthesizerSeptember 7, 2017 -
A Wideband Injection Locking Scheme and Quadrature GenerationSeptember 7, 2017 -
A Low-power 20Gb/s On-Chip LinkSeptember 7, 2017 -
A Fully Intraocular 512-channel Self-Calibrating Epiretinal ProsthesisSeptember 7, 2017 -

Contact
California Institute of Technology
M/C 136-93
1200 East California Boulevard
Pasadena, California 91125
CaltechMICS@gmail.com
Our lab is in the third floor of Moore Laboratory.

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A Fully Intraocular 512-channel Self-Calibrating Epiretinal Prosthesis A Wideband Injection Locking Scheme and Quadrature Generation