MICS Lab
  • Home
  • Research
  • Chip Gallery
  • Publications
  • People
  • Courses
  • News
  • MICS Social
  • Menu Menu
A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS

A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS

July 12, 2016/in VCSEL Driver /by awp-admin
/wp-content/uploads/2017/10/mics-logo-grey-100.png 0 0 awp-admin /wp-content/uploads/2017/10/mics-logo-grey-100.png awp-admin2016-07-12 09:36:472018-01-23 19:31:43A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS
MICS Caltech

Contact

California Institute of Technology
M/C 136-93
1200 East California Boulevard
Pasadena, California 91125
CaltechMICS@gmail.com
Our lab is in the third floor of Moore Laboratory.

Lab Member Login
Academic Calendar

Maps

  • Campus Map
  • Parking Map
  • Caltech Interactive Map
Caltech Aerial View
© Copyright - Mixed-mode Integrated Circuits and Systems Lab (MICS). Site: Academic Web Pages
Scroll to top