MICS Lab
  • Home
  • Research
  • Chip Gallery
  • Publications
  • People
  • Courses
  • News
  • MICS Social
  • Menu Menu
An 8 GHz First-order Frequency Synthesizer for Low-Power On-Chip Clock Generation

An 8 GHz First-order Frequency Synthesizer for Low-Power On-Chip Clock Generation

August 12, 2015/in Low-power First-order Frequency Synthesizer, On-Chip Interconnects /by awp-admin
/wp-content/uploads/2017/10/mics-logo-grey-100.png 0 0 awp-admin /wp-content/uploads/2017/10/mics-logo-grey-100.png awp-admin2015-08-12 10:41:572024-01-12 19:43:50An 8 GHz First-order Frequency Synthesizer for Low-Power On-Chip Clock Generation

A 20GB/s 136fJ/b 12.5Gb/s/μm On-Chip Link in 28nm CMOS

June 12, 2013/in On-Chip Interconnects /by awp-admin
/wp-content/uploads/2017/10/mics-logo-grey-100.png 0 0 awp-admin /wp-content/uploads/2017/10/mics-logo-grey-100.png awp-admin2013-06-12 10:22:272024-01-12 19:21:35A 20GB/s 136fJ/b 12.5Gb/s/μm On-Chip Link in 28nm CMOS
MICS Caltech

Contact

California Institute of Technology
M/C 136-93
1200 East California Boulevard
Pasadena, California 91125
CaltechMICS@gmail.com
Our lab is in the third floor of Moore Laboratory.

Lab Member Login
Academic Calendar

Maps

  • Campus Map
  • Parking Map
  • Caltech Interactive Map
Caltech Aerial View
© Copyright - Mixed-mode Integrated Circuits and Systems Lab (MICS). Site: Academic Web Pages
Scroll to top