MICS Lab
  • Home
  • Research
  • Chip Gallery
  • Publications
  • People
  • Courses
  • News
  • MICS Social
  • Menu Menu
24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication

24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication

February 10, 2013/in Low-Power Optical Interconnects /by awp-admin
/wp-content/uploads/2017/10/mics-logo-grey-100.png 0 0 awp-admin /wp-content/uploads/2017/10/mics-logo-grey-100.png awp-admin2013-02-10 08:02:042017-09-02 13:15:3324-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication

Ultra Low-Power Receiver Design for Dense Optical Interconnects

May 21, 2012/in Low-Power Optical Interconnects /by awp-admin
/wp-content/uploads/2017/10/mics-logo-grey-100.png 0 0 awp-admin /wp-content/uploads/2017/10/mics-logo-grey-100.png awp-admin2012-05-21 07:54:132017-09-02 13:15:45Ultra Low-Power Receiver Design for Dense Optical Interconnects

An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS for Ultra Low-power Optical Communication

March 1, 2012/in Low-Power Optical Interconnects /by awp-admin
/wp-content/uploads/2017/10/mics-logo-grey-100.png 0 0 awp-admin /wp-content/uploads/2017/10/mics-logo-grey-100.png awp-admin2012-03-01 07:51:222017-09-02 13:15:57An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS for Ultra Low-power Optical Communication
MICS Caltech

Contact

California Institute of Technology
M/C 136-93
1200 East California Boulevard
Pasadena, California 91125
CaltechMICS@gmail.com
Our lab is in the third floor of Moore Laboratory.

Lab Member Login
Academic Calendar

Maps

  • Campus Map
  • Parking Map
  • Caltech Interactive Map
Caltech Aerial View
© Copyright - Mixed-mode Integrated Circuits and Systems Lab (MICS). Site: Academic Web Pages
Scroll to top