MICS Lab
  • Home
  • Research
  • Chip Gallery
  • Publications
  • People
  • Courses
  • News
  • MICS Social
  • Menu Menu

Warning: Undefined array key 0 in /home/caltech/www/www/wp-content/themes/enfold-child/functions.php on line 37

Warning: Attempt to read property "slug" on null in /home/caltech/www/www/wp-content/themes/enfold-child/functions.php on line 37

Warning: Undefined array key 0 in /home/caltech/www/www/wp-content/themes/enfold-child/functions.php on line 38

Warning: Attempt to read property "slug" on null in /home/caltech/www/www/wp-content/themes/enfold-child/functions.php on line 38
An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS for Ultra Low-power Optical Communication

An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS for Ultra Low-power Optical Communication

Share this entry
  • Share on Facebook
  • Share on X
  • Share on Pinterest
  • Share on LinkedIn
  • Share on Tumblr
  • Share on Vk
  • Share on Reddit
  • Share by Mail
/wp-content/uploads/2017/10/mics-logo-grey-100.png 0 0 awp-admin /wp-content/uploads/2017/10/mics-logo-grey-100.png awp-admin2012-03-01 07:51:222024-01-12 19:45:56An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS for Ultra Low-power Optical Communication
Search Search
MICS Caltech

Contact

California Institute of Technology
M/C 136-93
1200 East California Boulevard
Pasadena, California 91125
CaltechMICS@gmail.com
Our lab is in the third floor of Moore Laboratory.

Lab Member Login
Academic Calendar

Maps

  • Campus Map
  • Parking Map
  • Caltech Interactive Map
Caltech Aerial View
© Copyright - Mixed-mode Integrated Circuits and Systems Lab (MICS). Site: Academic Web Pages
Link to: A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation Link to: A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation Link to: A 3×9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O Link to: A 3×9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O A 3×9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O
Scroll to top Scroll to top Scroll to top