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An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS for Ultra Low-power Optical Communication

An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS for Ultra Low-power Optical Communication

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/wp-content/uploads/2017/10/mics-logo-grey-100.png 0 0 awp-admin /wp-content/uploads/2017/10/mics-logo-grey-100.png awp-admin2012-03-01 07:51:222024-01-12 19:45:56An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS for Ultra Low-power Optical Communication
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Link to: A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation Link to: A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation Link to: A 3×9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O Link to: A 3×9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O A 3×9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O
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