A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS
A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS
/wp-content/uploads/2017/10/mics-logo-grey-100.png00awp-admin/wp-content/uploads/2017/10/mics-logo-grey-100.pngawp-admin2016-07-12 09:36:472024-01-12 19:56:52A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS
