Optical Chip-to-Chip and On-Chip Communication in CMOS

The focus of this project is the implementation of extremely dense arrays of transceivers for the future optical and hybrid interconnection systems. Novel circuit and system-level solutions are being used to achieve the lowest power per Gb/s, and the highest bandwidth per unit of area (for the target distance in the system).  Problems such as process variations, cross-talks in very dense arrays, noise and power consumption are tackled by approaches such as: reconfigurable IOs, cross-talk aware signaling and cross-talk cancellation techniques, all-digital and digitally-assisted circuits. Such high-performance transceivers will be able to support the high-bandwidth interconnects required by the future complex systems.