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On-Chip Communication
Networks and Clocking
With
the emergence of complex multi-core processors, and simultaneous
increase of data rates and resistance of the on-chip wires, the problem
of
low-power on-chip data communication has become crucial. In this
project we explore the design of a repeater-less transceiver for
signaling over long wires for point-to-point on-chip networks. In this
design
we use a single-tap low-power equalization at the receiver. An
effective low-swing
signaling is achieved at the transmitter with a pattern-dependent swing
control
circuit. The
first prototype is being implemented in a
CMOS 90nm technology, and achieves more than 10Gb/s of data rate over
1cm-long wires. |
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