High-Speed Electrical Chip-to-Chip Interconnects

The focus of this project is the design of low power interconnects that are critical components of the future multi-processors, severs, and other complex integrated systems. Fundamental limitations of high-speed signaling over bandwidth-limited channels are being investigated and solutions at the system-level as well as architecture and circuit-level are developed.

The current phase of the project includes an all-digital synchronization loop that uses a calibrated delay-line with a digital control to provide an infinite phase range without a conventional DLL or PLL. This technique removes the need for the analog loop filters and precise phase detectors. Moreover, the digitally controlled loop scales well with the technology. As part of this project we are also looking into analytical modeling and simulation methodologies for the design of an optimum low-noise font-end. The transciever supports more than 10Gb/s of data rate in 90nm CMOS.